The process of building an Integrated Circuit (IC) or integrated circuit chip typically involves physical implementation followed by verification. Part of this verification process involves static timing analysis. Often times, design changes require that blocks (e.g., components or groupings of components on the integrated circuit) be moved around to address gate growth or to address other floorplan needs. Unfortunately, these changes often have a negative impact on static timing closure. Because timing reports are textual, there is no easy way to see how far blocks can be moved before seeing a negative impact on timing without detailed analysis of the timing reports. This results in trial and error experimentation of various floorplans, which requires significant engineering attention which, in turn, results in wasted machine and license resource use and schedule delay.